Simulation and testing of controlled systems, such as plants or processes, which are desired to be controlled, and controllers that control them, can be a useful way to facilitate system design and creation in an efficient manner. The simulation and testing of a controlled system to optimize the system typically can save time and expense over actually implementing the controlled system and then attempting to optimize it. In a simulation, a controller and/or soft controller (e.g., controller emulator) can be associated with a desired simulated component(s) or process(es) to model a desired controlled system, wherein the design of the system, including the controller or soft controller, can be modified to optimize the system before actually implementing the system with a real component(s) or process(es). The controller and simulated components or processes each can be associated with respective clocks, wherein the simulation typically is performed in discrete steps (e.g., fixed steps) or time intervals. When desired (e.g., at the end of each step), data relating to events that occurred during the execution of the simulation over the desired time period can be exchanged between the controller and simulated components or processes, and the simulation can proceed to the next step, wherein the simulation can continue until a desired end point is reached.
During simulation, it can be desirable (e.g. necessary) to have synchronization of the various clocks and synchronization of the various data exchanges that occur as part of the simulation in order to accurately simulate the control system. Conventionally, an IEEE 1588 Precision Time Protocol (PTP) can be employed for synchronization in simulated control systems. The IEEE 1588 standards provide for a hierarchal master-slave architecture for clock distribution. When employing the IEEE 1588 standards, a clock in the system having the best quality is typically chosen to be the master clock. For instance, if a current master clock is based on ordinary time, and another clock in the system is then connected to a clock based on a Global Positioning System (GPS) system, which can be of higher quality than the ordinary time source of the current master clock, the clock associated with the GPS system can become the new master clock for the system.
In simulations, the respective clocks in the system are often unstable in relation to each other, as some clocks may run slower than other clocks during the simulation. To facilitate clock synchronization, typically, one clock associated with the system is selected to be a master clock, wherein it can be desirable to select the slowest clock to be the master clock. Often, the clock associated with a simulated component or process will be the slowest clock in the system, since the other clocks (e.g., slave clocks), which are faster, can be synchronized to the slowest clock.
Conventionally, simulation of smaller scale control systems, for example, using a single workstation and a single workstation simulation/control synchronization tool, has been achieved with some degree of success. However, today, many control systems are larger and more complex, and can comprise a number of subsystems that have to interact with each other. One problem with simulations of a larger, complex control system is that it is more difficult to synchronize clocks for the respective controllers and components, due in part to the complexity of distributed simulations with physical separation, which can result in the time progression of simulation nodes tending to run slower than wall clock time. For instance, depending on the system being simulated, during a time step, a first clock associated with a first simulated component may run slower than a second clock associated with a second simulated component; but during a subsequent time step, the first clock may run faster than the second clock. As a result, clock synchronization can be negatively impacted and the simulated system may never converge. Further, data exchange synchronization can be negatively impacted as well. The current IEEE 1588 standards are not effective in controlling clock synchronization and data exchange synchronization, in part because such synchronization tries to speed up the nodes in an attempt to advance (e.g., catch up) to synchronize with the master clock, which is operating at wall clock time. As a result, the system can never converge.
Another issue that can negatively impact system simulations is the variances in lengths of steps. For instance, if a 10 millisecond (ms) step is desired, a clock may run for more than 10 ms (e.g., 11 ms, 12 ms, 13 ms, . . . ) or less than 10 ms (e.g., 9 ms, 8 ms, 7 ms, . . . ), instead of the desired 10 ms. This issue and the problems with regard to unstable clocks in simulations of larger controlled systems can result in the system simulations taking a significantly longer time to be performed than desired. Currently, there is no way to efficiently simulate larger, more complex controlled systems, and no way to account for variances in the time lengths of steps in controlled system simulations, among other problems with conventional system simulations.
The above-described deficiencies of today's controlled system simulations are merely intended to provide an overview of some of the problems of conventional systems, and are not intended to be exhaustive. Other problems with the state of the art and corresponding benefits of some of the various non-limiting embodiments may become further apparent upon review of the following detailed description.